module top_module (
    input clk,
    input [2:0] y,
    input x,
    output Y0,
    output z
);

	always@(*)begin
		case(y)
			3'b000:begin
				z<=1'b0;
				Y0<=x;
			end
			3'b001:begin
				z<=1'b0;
				Y0<=~x;
			end
			3'b010:begin
				z<=1'b0;
				Y0<=x;
			end
			3'b011:begin
				z<=1'b1;
				Y0<=~x;
			end
			3'b100:begin
				z<=1'b1;
				Y0<=~x;
			end
			default:begin
                z<=z;
                Y0<=Y0;
            end
		endcase
	end
endmodule
